This invention relates to a charge transfer device and, more particularly, to a charge transfer device with a floating diffusion amplifier.
A typical example of the charge transfer device is disclosed in IEDM Technical Digest, 1973, page 24 and IEDM Technical Digest, 1974, page 55. FIGS. 1 and 2 illustrate the prior art charge transfer device. The prior art charge transfer device is fabricated on a p-type semiconductor substrate 101. In a major surface portion of the p-type semiconductor substrate 101 are formed lightly-doped n-type impurity regions 102 and n-type impurity regions 103 which are alternated with one another. The rightmost n-type impurity region is decreased in width, and is contiguous to the rightmost lightly-doped n-type impurity region. An n-type floating diffusion region 112 is provided between the rightmost lightly-doped n-type impurity region and a heavily-doped n-type impurity region 104. A heavily-doped p-type impurity region 105 surrounds the above-described n-type impurity regions 102/103/104 and the n-type floating diffusion region 112.
The major surface of the p-type semiconductor substrate 101 is covered with an insulating layer 106, and charge transfer electrodes 107a/107b/207a and 108a/108b/208a are electrically isolated from one another in the insulating layer 106. In order to make the charge transfer electrodes 107a/107b/207a/108a/108b/208a clear, any hatching line is not drawn in the cross section of the insulating layer 106 shown in FIG. 2.
The charge transfer electrodes 107a/107b/207a are respectively provided over the n-type impurity regions 103, and the charge transfer electrodes 108a/108b are provided over the lightly doped n-type impurity regions 102. The charge transfer electrodes 107a/107b/207a are partially overlapped with the charge transfer electrodes 108a/108b. A gate electrode 109 is provided over the rightmost lightly-doped n-type impurity region.
A clock signal "PHgr"1 is supplied from a metal line 111 to the charge transfer electrodes 107a/108a/207a/208a, and a clock signal "PHgr"2 is supplied to the charge transfer electrodes 107b/108b. A constant voltage VOG is supplied to the gate electrode 109. Thus, the charge transfer electrodes 107a, 207a and 107b are respectively paired with the adjacent charge transfer electrodes 108a, 208a and 108b, and the clock signals "PHgr"1 and "PHgr"2 are selectively supplied to the charge transfer electrode pairs 107a/108a, 207a/208a and 107b/108b. 
A gate electrode 110 is provided over the lightly-doped n-type impurity region between the floating diffusion region 112 and the heavily-doped n-type impurity region 104. A reset signal "PHgr"R is supplied to the gate electrode 110, and the floating diffusion region 112 is connected to an output circuit (not shown). The output circuit is implemented by a source follower, and the source follower achieves the impedance conversion.
FIGS. 3A, 3B and 3C illustrate potential wells created in the prior art charge transfer device during a charge transfer. Firstly, the reset signal "PHgr"R is applied to the gate electrode 110. Then, the potential barrier is removed from the lightly-doped n-type region under the gate electrode 110 as shown in FIG. 3A, and electric charge flows from the floating diffusion region 112 to the heavily-doped n-type impurity region 104. As a result, the floating diffusion region 112 becomes equal to the reset voltage VR. The clock signal "PHgr"1 is in the high level VH, and the other clock signal "PHgr"2 is in the low level VL (see FIG. 4). Charge packets e1 and e2 are accumulated in the potential well under the charge transfer electrode 208a and in the potential well under the charge transfer electrode 108a, respectively.
Subsequently, the reset signal "PHgr"R is removed from the gate electrode 110, and the potential barrier separates the floating diffusion region 112 from the heavily-doped n-type impurity region 104. The clock signals "PHgr"1 and "PHgr"2 are maintained at time t1, and the charge packets e1 and e2 are still accumulated in the potential well under the charge transfer electrode 208a and in the potential well under the charge transfer electrode 108a, respectively.
The clock signals "PHgr"1 and "PHgr"2 are respectively changed to the low level VL and the high level VH at time t2. Then, the potential well is created under the leftmost charge transfer electrode 108b, and a charge packet e3 flows into the potential well. The potential barrier is removed from the lightly-doped n-type impurity region under the charge transfer electrode 107b, and a potential well is created in the n-type impurity region under the charge transfer electrode 108b. Then, the charge packet e2 flows into the potential well in the n-type impurity region under the charge transfer electrode 108b as shown in FIG. 3C. Moreover, the bottom of the potential well under the charge transfer electrode 208a exceeds the potential barrier in the rightmost lightly-doped n-type impurity region under the gate electrode 109, and the charge packet e1 flows into the floating diffusion region 112.
The charge packet e1 varies the potential level in the floating diffusion region 112, and the potential variation is detected by the output circuit. The output circuit produces an output signal, the voltage level V of which is given as
V=Q/Cxc3x97G
where Q is the amount of charge of the charge packet e1, C is a capacitance coupled to the floating diffusion 112 and G is a voltage gain. Finally, the reset signal VR is applied to the gate electrode 110, again, and the potential barrier is removed from the lightly-doped n-type impurity region under the gate electrode 110. The floating diffusion region 112 is reset to the reset voltage VR. Thus, the charge packets e1, e2 and e3 are stepwise transferred to the floating diffusion region 112, and the output circuit produces the output signal from the potential variation in the floating diffusion region 112.
It is desirable to widely vary the potential level V of the output signal. As will be understood from the above equation, the smaller the capacitance C, the wider the variation of the potential level V. For this reason, the floating diffusion region 112 is much narrower than the n-type impurity regions 103 and 102 (compare the channel width W with the channel width Wxe2x80x2 FIG. 1). This is the reason the rightmost n-type impurity region contracts toward the rightmost lightly-doped n-type impurity region. As a result, the charge transfer electrode 208a has length Lxe2x80x2 longer than length L of the other charge transfer electrodes 108a and 108b, and signal charge accumulated around the oblique side lines flows over length Lxe2x80x3 greater than length Lxe2x80x2.
As described hereinbefore, the charge packets e1, e2 and e3 are transferred from the potential well to the next potential well in response to the clock signals "PHgr"1 and "PHgr"2. While the clock signal "PHgr"2 is staying at the high level VH, the charge packets are transferred from the potential well to the next potential well. When the clock signal "PHgr"2 is recovered from the low level VL to the high level VH, the potential well is isolated from the next potential well, and the charge transfer is completed. If the clock signal "PHgr"2 stays at the high level VH for a sufficiently long time, the charge packet is perfectly transferred to the next potential well without any residual charge. However, a high-speed charge transfer is required for a high-dense image pick-up device. As described hereinbefore, the signal charge in the central area of the leftmost n-type impurity region is moved over the length Lxe2x80x2, and the signal charge in the peripheral area is moved over the length Lxe2x80x3. The signal charge in the peripheral area is imperfectly transferred to the floating diffusion region 112, and residual signal charge is left in the potential well under the charge transfer electrode 208a. This results in a low charge transfer efficiency. When the prior art charge transfer device transfers a small amount of charge packet, the low charge transfer efficiency is serious.
It is therefore an important object of the present invention to provide a charge transfer device, which is improved in charge transfer efficiency.
To accomplish the object, the present invention proposes to create the final potential well closer to a floating diffusion region than other potential wells.
In accordance with one aspect of the present invention, there is provided a charge transfer device for conveying charge packets comprising a floating diffusion region having a first width and varied in potential level depending upon the amount of electric charge forming each of the charge packets, a charge transfer region including a transfer sub-region having a second width greater than the first width and a boundary sub-region contiguous to the floating diffusion region and decreased from the second width to the first width, plural charge transfer electrodes capacitively coupled to the transfer sub-region so as to create potential wells and potential barriers between the potential wells in the transfer sub-region and responsive to a driving signal for stepwise conveying the charge packets through the potential wells and a final charge transfer electrode capacitively coupled to the boundary sub-region so as to create a final potential well at a position in the boundary sub-region closer to the floating diffusion region than the remaining positions in the boundary sub-region and responsive to the driving signal for successively transferring the charge packets from one of the potential wells through the final potential well to the floating diffusion region.